`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:38:12 05/05/2012
// Design Name:   l2cache
// Module Name:   C:/achdmips/trunk/hdl/L2Cache/L2Test.v
// Project Name:  L2Cache
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: l2cache
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module L2Test;

	// Inputs
	reg clk;
	reg [31:0] l1_iside_addr;
	reg l1_iside_rd;
	reg l1_iside_wr;
	reg [3:0] l1_iside_wmask;
	reg [31:0] l1_iside_din;
	reg [31:0] l1_dside_addr;
	reg l1_dside_rd;
	reg l1_dside_wr;
	reg [3:0] l1_dside_wmask;
	reg [31:0] l1_dside_din;
	reg [31:0] mmu_din;
	reg mmu_dinok;

	// Outputs
	wire [31:0] l1_iside_dout;
	wire l1_iside_doutok;
	wire [31:0] l1_dside_dout;
	wire l1_dside_doutok;
	wire [31:0] mmu_addr;
	wire mmu_rd;
	wire mmu_wr;
	wire [31:0] mmu_dout;
	wire [3:0] mmu_wmask;

	// Instantiate the Unit Under Test (UUT)
	l2cache uut (
		.clk(clk), 
		.l1_iside_addr(l1_iside_addr), 
		.l1_iside_rd(l1_iside_rd), 
		.l1_iside_wr(l1_iside_wr), 
		.l1_iside_dout(l1_iside_dout), 
		.l1_iside_wmask(l1_iside_wmask), 
		.l1_iside_din(l1_iside_din), 
		.l1_iside_doutok(l1_iside_doutok), 
		.l1_dside_addr(l1_dside_addr), 
		.l1_dside_rd(l1_dside_rd), 
		.l1_dside_wr(l1_dside_wr), 
		.l1_dside_dout(l1_dside_dout), 
		.l1_dside_wmask(l1_dside_wmask), 
		.l1_dside_din(l1_dside_din), 
		.l1_dside_doutok(l1_dside_doutok), 
		.mmu_addr(mmu_addr), 
		.mmu_rd(mmu_rd), 
		.mmu_wr(mmu_wr), 
		.mmu_dout(mmu_dout), 
		.mmu_wmask(mmu_wmask), 
		.mmu_din(mmu_din), 
		.mmu_dinok(mmu_dinok)
	);

	reg ready = 0;
	initial begin
		// Initialize Inputs
		clk = 0;
		l1_iside_addr = 0;
		l1_iside_rd = 0;
		l1_iside_wr = 0;
		l1_iside_wmask = 0;
		l1_iside_din = 0;
		l1_dside_addr = 0;
		l1_dside_rd = 0;
		l1_dside_wr = 0;
		l1_dside_wmask = 0;
		l1_dside_din = 0;
		mmu_din = 0;
		mmu_dinok = 0;

		// Wait 100 ns for global reset to finish
		#100;
		ready = 1;
	end
	
	// Create clock input
	always begin
		#5;
		clk = ready;
		#5;
		clk = 0;
		if(ready)
			$display("--- CLOCK ---");
	end
	
	// Request Generator
	reg[15:0] testcount = 0;
	
	always @(posedge clk) begin
	
		l1_iside_addr <= 0;
		l1_iside_rd <= 0;
		l1_iside_wr <= 0;
		l1_iside_wmask <= 0;
		l1_iside_din <= 0;
		l1_dside_addr <= 0;
		l1_dside_rd <= 0;
		l1_dside_wr <= 0;
		l1_dside_wmask <= 0;
		l1_dside_din <= 0;
		
		case(testcount)
			
			0: begin
				$display("Test Case 0: DSIDE Uncached Write");
				testcount <= 1;
			end
			
			1: begin
				$display("Test Case 1: DSIDE Cached Write");
				testcount <= 2;
			end
			
			2: begin
				$display("Test Case 2: ISIDE Uncached Read");
				testcount <= 3;
			end
			
			3: begin
				$display("Test Case 3: DSIDE Uncached Read");
				testcount <= 4;
			end
			
			4: begin
				$display("Test Case 4: ISIDE/DSIDE Simultaneous Uncached Read");
				testcount <= 5;
			end
			
			5: begin
				$display("Test Case 5: ISIDE Cached Read");
				testcount <= 6;
			end
			
			6: begin
				$display("Test Case 6: DSIDE Cached Read");
				testcount <= 7;
			end
			
			7: begin
				$display("Test Case 7: ISIDE/DSIDE Simultaneous Cached Read");
				testcount <= 8;
			end
			
			8: begin
				$display("Test Case 8: ISIDE Cached Write (HIT)");
				testcount <= 9;
			end
			
			9: begin
				$display("Test Case 9: DSIDE Cached Write (HIT)");
				testcount <= 10;
			end
			
			10: begin
				$display("Test Case 10: ISIDE/DSIDE Simultaneous Cached Write (HIT/HIT)");
				testcount <= 11;
			end
			
			11: begin
				$display("Test Case 11: ISIDE/DSIDE Simultaneous Cached Write (MISS/HIT)");
				testcount <= 12;
			end
			
			12: begin
				$display("Test Case 12: ISIDE/DSIDE Simultaneous Cached Write (HIT/MISS)");
				testcount <= 13;
			end
			
			13: begin
				$display("Test Case 13: ISIDE/DSIDE Simultaneous Cached Write (MISS/MISS)");
				testcount <= 14;
			end
			
			14: begin
				$display("Test Case 14: ISIDE/DSIDE Simultaneous Cached Read (HIT/HIT)");
				testcount <= 15;
			end
			
			15: begin
				$display("Test Case 15: ISIDE/DSIDE Simultaneous Cached Read (HIT/MISS)");
				testcount <= 16;
			end
			
			16: begin
				$display("Test Case 16: ISIDE/DSIDE Simultaneous Cached Read (MISS/HIT)");
				testcount <= 17;
			end
			
			17: begin
				$display("Test Case 17: ISIDE/DSIDE Simultaneous Cached Read (MISS/MISS)");
				testcount <= 18;
			end
			
			18: begin
				// Stall
			end
			
		endcase
	end
	
endmodule

